TM 5-6675-320-14
(4) Read only memory 32 word constants.
Contains octal addresses 77ØØØ-
77Ø37.
The 32 word constants are located in ROM’s U7 and U6.
The eight least
significant bits (LSB’s), BUS 0 thru BUS 7, are located in U7, and the eight most
significant bits (MSB’s), BUS 8 thru BUS 15, are located in U6. Address lines ADR Ø
thru ADR 4 are used to address both ROM’s.
The low enable chip select (CS) for the ROM’s is derived from BUS 8, BUS 13, BUS 14,
read memory (RDMEM), and synchronous memory complete (SMC) signal lines.
The criteria for selecting ROM 32 word constants is as follows:
Address 8 high
Address 13 low
Address 14 low
Read memory (RDMEM) high
Synchronous memory complete (SMC) high
These signals, inputted to U2, U11, and U4, decode as ROM 32 select. U4 provides a
chip select to ROM’s U6 and U7 and disables bidirectional interface bus (BIB) driv-
ers U5 and U10, leaving the bus lines clear for ROM output.
c .
Internal I/0 PCA card A5.
I s f u n c t i o n a l l y d i v i d e d i n t o t w o c i r c u i t s:
I / 0 c i r c u i ts
I n t e r p o l a t o r c i r c u i ts
( 1 ) I / 0 c i r c u i t s .
Provide an interface between the front panel, interpolator
circuits, and PCA A3.
They perform two major functions:
Processor decoding
Processor interrupt
4-28
