TM 5-6675-320-14
Table 4-8. PCA A5 INTERPOLATOR WRITE MODE OPERATION SEQUENCE - Cont
Sequence
Step
C i r c u i t O p e r a t i on
8
Digital-to-analog converter (DAC) U12. Eight-bit multiplying DAC
U12 provides output current which is linear product of eight-bit
d i g i t a l i n p u t a n d a n a l o g i n p u t c u r r e n t . R e f e r e n c e c u r r e n t i s p r o-
vided by Q2 and determines full-scale output of DAC by setting
current through resistor ladder network in DAC. Full-scale adjust-
ment is provided by full-scale potentiometer R4. Current output
(10) from pin 4 is controlled by the setting of offset potentio-
meter R8 via transistor Q3.
The selected sine or cosine output
from the DAC is coupled to waveform compensator U3 via operational
amplifier U2.
9
10
11
12
13
Waveform compensators U1, U2, and U3. Waveform compensation is
accomplished by varying amount of third harmonic input to summing
junction at input of amplifier U2-2. Switch S1 in U3 is closed
during part of ROM third harmonic output which allows C7 to store
third harmonic.
Unity gain operational amplifier U1 couples third harmonic to X-
and Y-axis potentiometers R15 and R16. R15 and R16 control ampli-
tude to switches U3-S3 and U3-S4. Switch U3-S3 is closed when X-
axis is selected, and closing switch U3-S2 during ROM fundamental
output completes third harmonic feedback loop.
Output amplifier switching U4 and U21. Fundamental waveform
compensated by third harmonic forms DAC output from operational
amplifier U2.
It is sent to the output analog switch U4. U4-S2
and U4-S4 are closed sequentially by switch decoder U11. Switch
closure is timed to connect selected DAC output to its respective
operational amplifier in motor phase amplifier U21.
Capacitors C8 thru C11 hold level of amplifier input signal during
“switch open” times between subcycles.
F i e l d e f f e c t t r a n s i s t o r Q 4
ties analog common to digital common if pin 10 connector cable is
unplugged at J3.
Selected output of motor phase amplifier U21 is
coupled to its respective motor winding through motor drive cir-
cuitry located on PCA A8 and PCA A12.
Timing circuits U15, U16, U31, U32, and U20. The 5 MHz PHI clock
signal is coupled to input of dual 2- and 5-divider U16 through
nand gate U15.
Output of divider U16 is 250 kHz non-symmetrical
clock which is used to clock two cascaded synchronous four-bit
counters, U31 and U32.
These counters effectively divide 250 kHz
into 256 steps which are used as both input to control ROM U20 and
as enable signals to synchronize switch decoder U11, waveform com-
pensator U3 and ROM’s and U30.
Carry-out pulse from U31 is used
to set carry input to full adder U18 to Ø once every 16 clock
pulses, at beginning of each X- or Y-subcycle.
4-31
