TM 5-6675-320-14
MEMORY BLOCK(
ROM LSB
ROM MSB
OCTAL ADDRESSES
40
U15
U17
4Ø,ØØØ8-43,7778
44
U14
U16
44,ØØØ8-57,7778
(3) Read/Write memory.
Consists of 256 words of memory used for temporary
data storage by the processor.
The octal addresses for the 256-word RAM chips are
774ØØ-77777.
The bus bit pattern (inverted octal) for 774ØØ is ØØØ ØØØ Ø11 111 111,
which is now used to trace the RAM enabling signal circuitry.
(Table 4-7)
Table 47.
RAM ENABLE SEQUENCE
Step
C i r c u i t O p e r a t i o n
1
2
3
4
5
6a
6b
6C
INITIAL CYCLE
PCA A3 causes extended synchronous memory complete (EXSMC) to go
h i g h.
First of three high (1) outputs input to nand gate U4A.
A low (Ø) BUS 8 is clocked through latch U2. U2 outputs second
high to U4A.
A low BUS 13 and BUS 14 make U11 input a high to latch U2. High
is clocked through U2 to produce third high input to U4A-13.
U4A outputs low enable signal to pin 13 of RAM chips U19, U12, and
U13.
DURING A READ CYCLE
U4 also outputs low to bidirectional interface bus (BIB) drivers
U10 and U5.
Contents of memory are transferred onto bus.
DURING A WRITE CYCLE
PCA A3 sends read memory (RDMEM) low, causing nand gate U4 to out-
put high to U11 and BIB drivers U10 and U5.
High input to U11 causes it to output low write enable signal to
RAM chips U12, U13, U22, and U23.
High input to BIB drivers U10 and U5 transfers write data from bus
into memory (RAM chips U12, U13, U22, and U23).
4-27
