TM 5-6675-320-14
(c) Six clock periods are necessary for the microprocessor to accom-
plish a READ from memory, interpret and perform the instruction. Four more clock
periods are required to complete a WRITE from the microprocessor to RAM on PCA A4 or
a register on PCA A2 or A5.
NOTE
In order to troubleshoot hardware failures in the processing circuits,
i t i s n e c e s s a r y t o f o l l o w t h e f u n c t i o n o f t h e c i r c u i t r y i n t e r ms
of ROM phase timing when performing READ and WRITE operations.
See Table
4-6 which relates the timing operation of the processing circuits .
Table 4-6. PROCESSING CIRCUITS FUNCTIONAL SEQUENCE OPERATION
Clock
Period
O p e r a t i o n o f C i r c u i t
WRITE OPERATION
t1- t6
t7 -t9
Microprocessor tells RAM in which address to store data.
Data is transferred to be stored as follows:
t7
Microprocessor sets READ to low producing a high WRITE.
t8
start memory (STM) goes high which tells memory to stand by to
receive data.
‘ 9
extended synchronous memory complete (EXSMC) is generated.
Directs microprocessor to place data on data bus.
Microprocessor can also send data (write) to any of the following:
Registers on I/0 Interface PCA A2
Registers on HP-IB PCA A2
Self-test registers on PCA A3
Interrupt registers on PCA A3
Process of writing data to one of these other locations is accom-
plished in similar manner as described above. Correct register is
deactivated by register decoder which decodes data bits Ø-4.
A5 card decoder is activated by I/0 RAC, which is produced by
register decoder.
4-23
