TM 5-6675-320-14
Table 4-8. PCA A5 INTERPOLATOR WRITE MODE OPERATION SEQUENCE - Cont
Sequence
Step
C i r c u i t O p e r a t i on
14
Carry-out pulse from counter U32 occurs once every millisecond.
It is used as interrupt request (IRQ) signal which is the enable
s i g n a l f o r i n t e r r u p t ( I n t ) c i r c u i t r y i n I / O s e c t i o n o f t h i s P C A.
Control ROM U20 decodes counter’s output and provides control sig-
nals to switch decoder U11 and output analog switch U4, and also
provides synchronizing signals to control flow of data through U3,
U10, U19, U27, and U28.
b . P r o c e s s o r i n t e r r u p t .
An interrupt (INT) signal is generated by interrupt
r e q u e s t c i r c u i t r y o f t h e I / O c i r c u i t s .
It synchronizes data requests from the
i n t e r p o l a t o r c i r c u i t s w i t h t h e p r o c e s s o r s y s t e m.
This INT signal causes PCA A3 to
i n t e r r u p t w h a t e v e r i t i s p r o c e s s i n g , s e r v i c e t h e i n t e r p o l a t o r r e q u e s t f o r d a t a , a n d
then continue processing from the point at which it was interrupted. The interpola-
tor section requests new velocity information for the motors every millisecond.
( 1 ) T h e i n t e r r u p t c i r c u i t r y o f t h e I / O c i r c u i t s h a s t w o m a i n s t a g e s :
I n t e r r u p t s y s t e m e n a b l e l a t c h c i r c u it
I n t e r r u p t s y n c h r o n i z i n g ( s y n c ) c i r c u it
(a) The interrupt system enable latch circuit consists of cross-coupled
gates U24 and U15.
When enabled, they cause PCA A3 to recognize an interrupt
request.
T h i s l a t c h , a n d t h e i n t e r r u p t s y s t e m , i s d i s a b l e d ( i n h i b i t e d ) d u r i ng
power-up (PUP) or by a software command that is decoded by register decoder U23 as a
read register 15 (RD15).
The latch is enabled by a write register 15 (WR15) command
being decoded by register decoder U23.
(b) The interrupt synchronizing (SYNC) circuit has an interrupt request
flip-flop U25 which samples the state of interrupt enable latch U24 each time U25 is
c l o c k e d b y t h e l e a d i n g e d g e o f t h e i n t e r p o l a t o r i n t e r r u p t r e q u e s t ( I R Q ) s i g n a l . If
i n t e r r u p t e n a b l e l a t c h U 2 4 i s e n a b l e d , t h e Q - o u t p u t o f i n t e r r u p t r e q u e s t f l i p - f l op
U25 will go high, signifying that a valid interrupt request is to be sent to PCAA3 .
The output of the interrupt request flip-flop U25 is clocked through the interrupt
sync flip-flop by the leading edge of the instruction fetch start memory (IFSTM) to
synchronize the interrupt request with the processor system timing. Nand gate U24A
gates the IFSTM, the synchronized IRQ and the latched IRQ to provide the proper
interrupt (INT) signal state to PCA A3.
I n t e r r u p t r e q u e s t f l i p - f l o p U 2 5 i s p r e s et
during power-up (PUP) or when the processor generates an interrupt acknowledge (IAK)
s i g n a l .
4-32
