TM 5-6675-320-14
( a ) P r o c e s s o r d e c o d i n g .
PCA A5 decodes a control data word from PCA
A3 .
The microprocessor on PCA A3 sends the encoded control data word via lines AØ1
thru AØ2 and generates a start memory (STM) true signal which gates U22 on PCA A5.
D a t a AØ1 t h r u AØ2 are gated to register decoder U23. An I/0 register
access line (RAC) false signal and synchronous memory complete (SMC) true signal
from the microprocessor on PCA A3 allows the control data word to be decoded by U23.
An output I/0 RAL signal from U23 signifies a memory access to an I/0 register. An
SMC signal is a system timing signal which signifies data on the bus is true. The
decoded word instructs PCA AS to enter into one of four possible modes:
Front panel read RD17
Front panel write WR17
Pen stable read RD16
Interpolator write WR16
(b) If the encoded data word selects the front panel read (FPRD) mode
RD17, decoder U23 allows the front panel switch data to be placed on the bus by
enabling bidirectional interface bus (BIB) drivers U5, U8, and U13.
(c) If front panel write (FPWR) mode WR17 is selected (at U23-7), the
status of the pen position and the four front panel indicators is stored in hex D-
t y p e f l i p - f l o p U 7 .
The four front panel indicator lamps, LOAD, ENTER, WINDOW, and
ERROR, are turned on by data signals from PCA A3. Decoder U23-7 clocks the
appropriate low data bit from the bus through hex D-type flip-flop U7 to the selected
lamp circuit turning on the associated lamp.
(d) In pen stable read mode RD16, buffer drivers U6 and U14 perform an
interface function between PCA A7 and the bus.
Selection of register 16 (RD16) pen
stable read causes decoder U23 to output a low enable signal to buffer drivers U6
and U14 allowing pen select, pen armed,
and stable status data to be driven onto the
bus.
(e) Interpolator write mode WR16 is selected via write interpolator
r e g i s t e r 1 6 .
This causes decoder U23 to output a low enable signal to both data
latch U9 and the power high flip-flop U19 in the interpolator section. For a de-
tailed description of the interpolator write mode, see Table 4-8.
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