TM 5-6675-320-14
Table 4-6. PROCESSING ClRCUITS FUNCTIONAL SEQUENCE OPERATION - Cont
Clock
Period
O p e r a t i o n o f C i r c u it
WRITE OPERATION - Cont
NOTE
Register 10 (U10 and U11) latches (reads) last data bus word before
i n t e r r u p t o c c u r s .
Data word is latched until interrupt acknowledge is
complete and then places data back into bus.
tl a n d t2
Microprocessor U23 sets SYNC high to initiate instruction fetch.
Sets PDR high to indicate that it has placed address on data bus
(IDA Ø-15).
t3
Microprocessor sets start memory (STM) and register access line
(RAL) high.
STM (high) enables interface bus drivers U30 and U31
to interface (internal) data bus with ROM phase inputs. Data
bits 13 and 14 low are decoded by U19 to mean ROM phase read.
(IFSTM is also generated but is only used by I/O to synchronize
i n t e r r u p t w i t h b e g i n n i n g o f i n s t r u c t i o n f e t c h .)
t4 a n d t5
Interface bus transceivers (IBT’s) are selected to drive data bus
from microprocessor direction.
C h i p s e l e c t c i r c u i t s a r e a c t i v a t e d
and data is transferred to microprocessor.
These functions are
accomplished by setting extended synchronous memory complete
(EXSMC), PDR, and start memory (STM) high at ROM phase. (Note that
EXSMC is also used for timing of external memory access on PCA A4.)
Chip select enables ROM phase (U21 and U22) allowing it to place
any instruction, that occupies addressed memory, onto data bus.
4-24
READ OPERATION
