TM 5-6675-320-14
Table 4-8. PCA A5 INTERPOLATOR WRITE MODE OPERATION SEQUENCE
Sequence
Step
C i r c u i t O p e r a t i on
1
Read/Write register U9.
When the interpolator write line of the
control bus goes low, it enables the write function of registers
U9-12.
Data buses 12-15 are latched into one of four registers
selected by two address bits on buses Ø and 1.
At start of interpolator operating cycle, registers U9-RB and RA
are low and four least significant bits (LSB’s) of the X-axis in-
struction appear on both the output pins of register U9 and input
pins of data selector U17.
6
Data selector U17.
High input select signal from U17 transfers X-
LSB to full adder U18.
Four-Bit and carry adder U18 and U19. Output of full adder U18 is
the sum of X-LSB from previous instruction stored in accumulator
U27.
The summation is then transferred to X-LSB register in accu-
mulator U27.
Write enable decoder U10.
The data transfer from full adder U18 to
X-accumulator U27 is initiated by gating clock pulse through nand
gate from U20 to U10.
Write signal from ROM control gates clock
pulse through nand gate U10.
U10 goes low and enables write func-
tion of accumulator U27.
Accumulators U27 and U28.
Having stored X-LSB in accumulator U27,
X-MSB is now clocked through data latch U9 and data selector U17 to
inputs of adder U18.
At same time, MID-SB signal from accumulator
U27 is clocked through data selector U26 to inputs of adder U18.
Output of adder U18 is restored in MID-SB of accumulator U27.
With next clock pulse, output of register U9 remains same while
select input to data selector U17 couples MSB sign bit (line 6) to
inputs of adder U18.
At same time, four MSB’s are coupled from U28
through U26 to inputs of adder U18. Output of adder U18 is now
latched into MSB of U28.
This completes first subcycle, and output
of accumulators U27 and U28 remains constant while data is being
transferred into sine/cosine ROM’s U29 and U30. Four LSB' S a n d
MSB’s (sign bits) are discarded .
Sine and cosine only memories U29 and U30. Output function of
sine/cosine ROM’s U29 and U30 is selected by state of inputs from
control ROM U20.
Outputs from ROM U30 make up four LSB inputs to
digital-to-analog converter (DAC) U12 while the outputs from ROM
U29 provide four MSB inputs to DAC U12.
4-30
2
3
4
5
7
