TM 5-6675-323-14
OCTAL ADDRESSES
ROM MSB
MEMORY BLOCK
ROM LSB
U17
U15
40
4 , 8-43,777 8
U16
U14
44
4 4 , 8- 5 7 , 7 7 7 8
( 3 ) R e a d / W r i t e m e m o r y . C o n s i s t s of 256 words of memory used for temporary
d a t a s t o r a g e b y t h e p r o c e s s o r . T h e octal addresses for the 256-word RAM chips are
T h e bus bit pattern (inverted octal) for 774 is 11 111 111,
774-77777.
(Table 3-7)
which is now used to trace the RAM enabling signal circuitry.
RAM ENABLE SEQUENCE
Table 3-7.
Circuit Operation
Step
INITIAL CYCLE
PCA A3 causes extended synchronous memory complete (EXSMC) to go
1
high.
First of three high (1) outputs input to nand gate U4A.
A low () BUS 8 is clocked through latch U2. U2 outputs second
2
high to U4A.
3
A low BUS 13 and BUS 14 make U11 input a high to latch U2. High
is clocked through U2 to produce third high input to U4A-13.
4
U 4 A outputs low enable signal to pin 13 of RAM chips U19, U12, and
U13.
DURING A READ CYCLE
5
U4 also outputs low to bidirectional interface bus (BIB) drivers
5
U10 and U5. C o n t e n t s o f m e m o r y a r e t r a n s f e r r e d o n t o b u s .
DURING A WRITE CYCLE
PCA A3 sends read memory (RDMEM) low, causing nand gate U4 to out-
6a
p u t high to U11 and BIB drivers U10 and U5.
High input to U11 causes it to output low write enable signal to
6b
RAM chips U12, U13, U22, and U23.
H i g h input to BIB drivers U10 and U5 transfers write data from bus
6C
into memory (RAM chips U12, U13, U22, and U23).
3-27
