TM 5-6675-323-14
(c) Six clock periods are necessary for the microprocessor to accom-
plish a READ from memory, interpret and perform the instruction. Four more clock
p e r i o d s are required to complete a WRITE from the microprocessor to RAM on PCA A4 or
a register on PCA A2 or A5.
NOTE
In order to troubleshoot hardware failures in the processing circuits,
it is necessary to follow the function of the circuitry in terms
of ROM phase timing when performing READ and WRITE operations.
See Table
3-6 which relates the timing operation of the processing circuits.
Table 3-6. PROCESSING CIRCUITS FUNCTIONAL SEQUENCE OPERATION
Clock
Period
Operation of Circuit
WRITE OPERATION
Microprocessor tells RAM in which address to store data.
Data is transferred to be stored as follows:
M i c r o p r o c e s s o r sets READ to low producing a high WRITE.
t
7
s t a r t memory (STM) goes high which tells memory to stand by to
t
8
receive data.
e x t e n d e d synchronous memory complete (EXSMC) is generated.
t
9
Directs microprocessor to place data on data bus.
Microprocessor can also send data (write) to any of the following:
R e g i s t e r s on I/O Interface PCA A2
Registers on HP-IB PCA A2
Self-test registers on PCA A3
I n t e r r u p t registers on PCA A3
Process of writing data to one of these other locations is accom-
Correct register is
plished in similar manner as described above.
d e a c t i v a t e d b y r e g i s t e r d e c o d e r w h i c h d e c o d e s d a t a bits ~-4.
A 5 card decoder is activated by I/O RAC, which is produced by
register decoder.
3-23
