TM 5-6675-323-14
b. Memory PCA card A4.
Consists of two functional units: the BIB drivers and
the memory.
The bidirectional interface bus (BIB) drivers provide interface between the TTL bus
and the MOS memory bus. When memory 40, memory 44, or the RAM are accessed during
D u r i n g the WRITE cycle for the RAM or a
a READ cycle, the BIB drives the TTL bus.
R E A D cycle for the ROM, the BIB drives the MOS memory bus. The major control lines
that determine direction of the BIB drivers are the read memory (RDMEM) and the HI
PAGE lines.
T h e memory portion of PCA A4 includes the following:
M e m o r y access decoding and address latching
Read only memories 40 and 44
R e a d / w r i t e memory
Read only memory 32 word constants
(1) Memory access decoding and address latching. Decodes signals from PCA
A 3 and the bus data to enable and access the memory location selected. A low BUS
1 4 indicates that a memory location on the memory PCA is to be addressed. When the
H I PAGE line is made true by a low BUS 13 and BUS 14, the state of BUS 8 determines
w h e t h e r the RAM or the ROM 32 word constants are to be accessed, and the state of
b u s 11 determines whether memory 40 or memory 44 is to be enabled. The word in
m e m o r y to be addressed is specified by decoding bus bits -10. Although the plotter
h a s a total of 5K of ROM, only 4K is located on the memory PCA. The remaining 1K of
R O M is located on PCA A3 to allow the processor PCA to operate independently when
in the self-test mode of operation from the system and, thus, simplify troubleshoot-
ing of the processor PCA.
F o u r control signals from PCA A3 determine when PCA A4 is to be accessed and the
d i r e c t i o n o f t h e b u s d r i v e . They are:
s t a r t memory (STM), extended synchronous
memory complete (EXSMC), read memory (RDMEM), and synchronous memory complete (SMC).
T o select memory 40 (U15 and U17), a high BUS 11 is clocked through U2 by the
l e a d i n g edge of the STM signal. T h i s causes ADR 11 to output a low enable signal to
c h i p select (CS) pin 18 or both U15 and U17 (memory 40). Likewise, a low BUS 11
will make ADR 11 high and enable memory 44.
BUS 11 = 1 = Selects Memory 40 (U15 and U17)
To summarize:
BUS 11 = = Selects Memory 44 (U14 and U16)
H o w e v e r , during the READ cycle when memory 40 or 44 is to be addressed, U1 provides
I f address 11 is low, ROM 40 is selected
a low chip select to U15, U14, and U16.
(U15 and U17).
I f address 11 is high, ROM 44 is selected (U14 and U16).
C o n s i s t s of 4K memory blocks in which
( 2 ) Read only memories 40 and 44.
Each block (40 and 44) consists of
the instructions for the processor are stored.
the first containing the eight least significant bits
two 2K x 8 memory chips:
(LSB's) of a data word and the second containing the eight most significant bits
( M S B)S ) . ( S e e t a b l e w h i c h f o l l o w s . )
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