TM 5-6675-323-14
PCA A5 decodes a control data word from PCA
(a) Processor decoding.
A3 . T h e microprocessor on PCA A3 sends the encoded control data word via lines A 1
thru A 2 and generates a start memory (STM) true signal which gates U22 on PCA A5.
D a t a A 1 t h r u A 2 a r e g a t e d t o r e g i s t e r d e c o d e r U 2 3 . A n I / O r e g i s t e r
access line (RAC) false signal and synchronous memory complete (SMC) true signal
f r o m the microprocessor on PCA A3 allows the control data word to be decoded by U23.
A n output I/O RAL signal from U23 signifies a memory access to an I/O register. An
SMC signal is a system timing signal which signifies data on the bus is true. The
decoded word instructs PCA A5 to enter into one of four possible modes:
F r o n t panel read RD17
F r o n t panel write WR17
Pen stable read RD16
Interpolator write WR16
( b ) If the encoded data word selects the front panel read (FPRD) mode
R D 1 7 , decoder U23 allows the front panel switch data to be placed on the bus by
enabling bidirectional interface bus (BIB) drivers U5, U8, and U13.
( c ) If front panel write (FPWR) mode WR17 is selected (at U23-7), the
status of the pen position and the four front panel indicators is stored in hex D-
t y p e f l i p - f l o p U 7 . T h e four front panel indicator lamps, LOAD, ENTER, WINDOW, and
E R R O R , are turned on by data signals from PCA A3. Decoder U23-7 clocks the
appropriate low data bit from the bus through hex D-type flip-flop U7 to the selected
lamp circuit turning on the associated lamp.
( d ) In pen stable read mode RD16, buffer drivers U6 and U14 perform an
S e l e c t i o n of register 16 (RD16) pen
i n t e r f a c e function between PCA A7 and the bus.
stable read causes decoder U23 to output a low enable signal to buffer drivers U6
a n d U14 allowing pen select, pen armed, and stable status data to be driven onto the
bus.
(e) Interpolator write mode WR16 is
selected via write interpolator
r e g i s t e r 1 6 . T h i s causes decoder U23 to output a
low enable signal to both data
latch U9 and the power high flip-flop U19 in the
interpolator section. For a de-
tailed description of the interpolator write mode,
see Table 3-8.
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