TM 5-6675-323-14
Table 3-6. PROCESSING CIRCUITS' FUNCTIONAL SEQUENCE OPERATION - Cont
Clock
Period
Operation of Circuit
WRITE OPERATION - Cont
NOTE
Register 10 (U10 and Ull) latches (reads) last data bus word before
interrupt occurs. Data word is latched until interrupt acknowledge is
complete and then places data back into bus.
READ OPERATION
Microprocessor U23 sets SYNC high to initiate instruction fetch.
S e t s PDR high to indicate that it has placed address on data bus
(IDA 0-15).
Microprocessor sets start memory (STM) and register access line
( R A L ) h i g h . S T M (high) enables interface bus drivers U30 and U31
to interface (internal) data bus with ROM phase inputs. Data
bits 13 and 14 low are decoded by U19 to mean ROM phase read.
( I F S T M is also generated but is only used by 1/0 to synchronize
interrupt with beginning of instruction fetch.)
Interface bus transceivers (IBT's) are selected to drive data bus
from microprocessor direction. Chip select circuits are activated
a n d d a t a i s t r a n s f e r r e d t o m i c r o p r o c e s s o r . T h e s e functions are
a c c o m p l i s h e d by setting extended synchronous memory complete
( E X S M C ) , PDR, and start memory (STM) high at ROM phase. (Note tha <
EXSMC is also used for timing of external memory access on PCA A4.
C h i p select enables ROM phase (U21 and U22) allowing it to place
any instruction, that occupies addressed memory, onto data bus.
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