TM 5-6675-323-14
Table 3-8. PCA A5 INTERPOLATER WRITE MODE OPERATION SEQUENCE - Cont
Sequence
Step
Circuit Operation
14
Carry-out pulse from counter U32 occurs once every millisecond.
It is used as interrupt request (IRQ) signal which is the enable
signal for interrupt (Int) circuitry in I/O section of this PCA.
Control ROM U20 decodes counter's output and provides control sig-
n a l s to switch decoder U11 and output analog switch U4, and also
provides synchronizing signals to control flow of data through U3,
U10, U19, U27, and U28.
b.
Processor interrupt. An interrupt (INT) signal is generated by interrupt
request circuitry of the I/O circuits.
It synchronizes data requests from the
i n t e r p o l a t o r c i r c u i t s w i t h t h e p r o c e s s o r s y s t e m . T h i s INT signal causes PCA A3 to
interrupt whatever it is processing, service the interpolator request for data, and
then continue processing from the point at which it was interrupted. The interpola-
tor section requests new velocity information for the motors every millisecond.
(1) The interrupt circuitry of the I/O circuits has two main stages:
Interrupt system enable latch circuit
Interrupt
synchronizing
(sync)
circuit
(a) The interrupt system enable latch circuit consists of cross-coupled
gates U24 and U15. W h e n enabled, they cause PCA A3 to recognize an interrupt
request.
This latch, and the interrupt system, is disabled (inhibited) during
p o w e r - u p (PUP) or by a software command that is decoded by register decoder U23 as a
r e a d r e g i s t e r 1 5 ( R D 1 5 ) . T h e latch is enabled by a write register 15 (WR15) command
b e i n g decoded by register decoder U23.
(b) The interrupt synchronizing (SYNC) circuit has an interrupt request
f l i p - f l o p U25 which samples the state of interrupt enable latch U24 each time U25 is
clocked by the leading edge of the interpolator interrupt request (IRQ) signal. If
interrupt enable latch U24 is enabled, the Q-output of interrupt request flip-flop
U25 will go high, signifying that a valid interrupt request is to be sent to PCA A3.
The output of the interrupt request flip-flop U25 is clocked through the interrupt
sync flip-flop by the leading edge of the instruction fetch start memory (IFSTM) to
synchronize the interrupt request with the processor system timing.
Nand gate U24A
g a t e s the IFSTM, the synchronized IRQ and the latched IRQ to provide the proper
interrupt (INT) signal state to PCA A3.
Interrupt request flip-flop U25 is preset
during power-up (PUP) or when the processor generates an interrupt acknowledge (IAK)
signal.
3-32
