TM 5-6675-323-14
Table 3-4. PCA A2 ACCEPTOR HANDSHAKE MODE OPERATION - Cont
Sequence
Step
Circuit and Signal Operation
I N I T I A T I O N - Cont
8
U4 and U5 receive and decode bits 6 and 7 from U33. BIT 6 true and
B I T 7 false signals decode as listen handshake mode, and listen de-
code clock pulse is sent to listen flip-flop U17A.
9
U 1 6 , U4, and U26 decode bits 1-5 to provide CLK input to listen
flip-flop U17A. Any combination of data bits 1-5 will decode to
produce true input to CLK, except bit 11111 which decodes as false.
10
A d d r e s s comparator U20 compares bits 1-5 from computer to five bits
f r o m preset ADDRESS switch S1 on PCA A1. If bits are same, then
U 2 0 generates my address to indicate that plotter is being addres-
sed.
11
Listen flip-flop U17A receives CLK input from decoded bits 1-5,
receives input from my address and is clocked from decoded bits 6
and 7.
This sets U17A which generates listen (LST) bit.
12
U 1 9 C is set by LST and generates receive handshake (RHS). RHS is
s e n t to PCA A3 on bus 14 via microprocessor input gate U12. LST
also sets data accepted (DAC) true and ready for data (RFD) false.
13
U 8 receives DAC true and RFD false from U19 and transmits it to
c o m p u t e r . C o m p u t e r responds by sending data available (DAV) false
to U8.
14
U 8 transmits data available (DAV) false to microprocessor on PCA A3
T h i s removes receive handshake (RHS)
v i a U22 and to U19 via U24.
input from microprocessor.
15
U 6 , U27, and U19 receive DAV false and set DAV false and ready for
data (RFD) true.
TRANSFER OF DATA
1
Computer places data byte on data bus via U33 and U7.
2
C o m p u t e r sets DAV true at U8.
3
U 6 , U27, and U19 set RFD false.
4
M i c r o p r o c e s s o r on PCA A3 clocks microprocessor input gates U11 and
U 1 2 and accepts data on data bus.
U 6 , U27, and U19 set data accepted (DAC) true.
5
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