TM 5-6675-320-14
Table 4-4. PCA A2 ACCEPTOR HANDSHAKE MODE OPERATION - Cont
Sequence
Step
Circuit and Signal Operation
INITIATION - Cont
8
U4 and U5 receive and decode bits 6 and 7 from U33. BIT 6 true and
BIT 7 false signals decode as listen handshake mode, and listen de-
code clock pulse is sent to listen flip-flop U17A.
9
U16, U4, and U26 decode bits 1-5 to provide CLK input to listen
f l i p - f l o p U 1 7 A .
Any combination of data bits 1-5 will decode to
produce true input to CLK, except bit 11111 which decodes as false.
10
Address comparator U20 compares bits 1-5 from computer to five bits
from preset ADDRESS switch S1 on PCA A1. If bits are same, then
U20 generates my address to indicate that plotter is being addres-
sed.
11
12
13
14
15
1
2
3
4
5
Listen flip-flop U17A receives CLK input from decoded bits 1-5,
receives input from my address and is clocked from decoded bits 6
and 7.
This sets U17A which generates listen (LST) bit.
U19C is set by LST and generates receive handshake (RHS). RHS is
sent to PCA A3 on bus 14 via microprocessor input gate U12. LST
also sets data accepted (DAC) true and ready for data (RFD) false.
U8 receives DAC true and RFD false from U19 and transmits it to
computer.
Computer responds by sending data available (DAV) false
to U8.
U8 transmits data available (DAV) false to microprocessor on PCA A3
via U22 and to U19 via U24.
This removes receive handshake (RHS)
input from microprocessor.
U6, U27, and U19 receive DAV false and set DAV false and ready for
data (RFD) true.
TRANSFER OF DATA
Computer places data byte on data bus via U33 and U7.
Computer sets DAV true at U8.
U6, U27, and U19 set RFD false.
Microprocessor on PCA A3 clocks microprocessor input gates U11 and
U12 and accepts data on data bus.
U6, U27, and U19 set data accepted (DAC) true.
4-18
