TM 5-6675-323-14
(2) The output from U24 is loaded into the four LSB registers of the X
T h e data transfer to U19 is accomplished when U19 is enabled by
a c c u m u l a t o r U19.
t h e w r i t e e n a b l e d e c o d e r U 1 0 . T h e decoder is enabled by the clock signal and a
write signal from control ROM U20.
(3) Having stored the X-axis LSB in U19, the X-axis most significant bits
These are summed with the X MID SB from the
( M S B ) are loaded into the adder U24.
p r e c e d i n g subcycle and stored in the MID SB register of U19. With the next clock
pulse, the output of the data register remains constant. The data selector U26
c o u p l e s the sign bit of the MSB to the Y input of the adder U24, while the MSB from
the previous subcycle is coupled to the Z input. These bits and the sign bit are
s u m m e d and latched into the MSB register of U16 by the write enable decoder U10C.
This completes the updating of the X-axis accumulator for this subcycle.
( 4 ) The output of the accumulators is used to address the sine/cosine ROMs
U9 and U15. T h e four LSBs and the sign bit of the MSB are not used to address the
ROMs, but are retained for use in further computation. The output function of the
R O M s is controlled by the inputs to pins 14 and 15. See Table 3-16. ROM U9 gene-
rates the four LSB inputs to the digital to analog converter (DAC) U7, while U15
o u t p u t s the four MSBs to U7.
Table 3-16. ROM FUNCTIONS
ROM OUTPUT
PIN 14
PIN 15
C o s i n e , 3rd Harmonic
Low
Low
C o s i n e Fundamental
High
Low
S i n e , 3rd Harmonic
Low
High
S i n e Fundamental
High
High
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