TM 5-6675-323-14
Table 3-14. MICROPROCESSOR DEFINITIONS - Cont
Definition
Name
Mnemonic
A self-test switch input which, when actu-
FLG
FLAG
ated, causes system to go to the next step.
STS
STATUS
I n d i c a t e s on power-up whether the system is
in normal operation or self-test.
A signal where the rising edge denotes
IFSTM
INSTRUCTION FETCH
START MEMORY
address of an instruction.
A c k n o w l e d g e s that an interrupt has been
IAK
INTERRUPT (READ 10)
accepted.
ACKNOWLEDGE
XSMC
EXTENDED SYNCHRONOUS
Extends the SMC to allow time needed by MOS
memories to stabilize data.
MEMORY COMPLETE
s. C l o c k g e n e r a t o r . T h e o u t p u t o f t h e c r y s t a l c o n t r o l l e d 1 0 M H z o s c i l l a t o r
provides the clock input for the divide by two flip-flop U60A which in turn provides
two 5 MHz pulsed inputs to the clock driver circuit. The clock driver U63 outputs
a r e MOS level non-overlapping clock pulses referred to as phase 1 (PH1) and phase 2
(PH2).
These two signals provide all timing for the plotter and the clock drive to
the microprocessor.
t . Microprocessor.
Using the clock input, the microprocessor issues the appro-
priate timing signals to initiate and maintain the proper sequence of events re-
quired for processing data and instructions. The activities of the microprocessor
a r e c y c l i c a l ; fetching an instruction, performing the required operations, and then
fetching the next instruction in an orderly, timed sequence.
(1) The main timing signal from the microprocessor is start memory (STM),
i n d i c a t i n g t h e s t a r t o f a m e m o r y r e a d c y c l e . T h e falling edge of STM is used to
l a t c h the memory address into the 3-state address latches U52 and U53. The rising
e d g e of synchronous memory complete (SMC) indicates the end of memory access cycle,
with the data being latched into either the microprocessor (READ cycle) or into RAM
( W R I T E cycle).
In order to satisfy the access time requirements of RAM and some of
t h e internal I/O circuitry, SMC is extended by the use of unsynchronous memory
c o m p l e t e UMC to generate extended synchronous memory complete (XSMC). The micropro-
cessor bus is buffered by the use of bidirectional drivers U46 and U47. The MOS
(memory) bus is further isolated from the TTL bus by the use of bidirectional
d r i v e r s U49 and U50.
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