TM 5-6675-323-14
a d . M e m o r y c o n t r o l l o g i c . T h e 15-bit memory address register consists of two 8-
bit bistable latches, U52 and U53, which latch the address off the plotter bus on
t h e rising edge of STM. T h e f i r s t 1 3 o u t p u t s a r e s u p p l i e d t o t h e 8 k R O M s t o s e l e c t
s p e c i f i c m e m o r y l o c a t i o n s . The ROMs are enabled by addresses 13 and 14 along with
STM, READ, and R10 + RAL. T h e R A M a d d r e s s l o c a t i o n s a r e a c c e s s e d b y t h e f i r s t
1 0 o u t p u t s o f t h e a d d r e s s r e g i s t e r . T h e devices are enabled by addresses 10 and 14
along with XSMC.
T h e READ line determines if a READ or WRITE function is occurring.
ac. M a i n P C A A 2 i n t e r p o l a t o r c i r c u i t r y . T h e i n t e r p o l a t o r c i r c u i t r y o f t h e m a i n
P C A receives the X- and Y-velocity data from the processor, integrates, and converts
the data into analog signals for the motor driver circuits.
During the 1024 microsecond operating cycle, the motor position is updated eight
times.
This is accomplished by adding 1/8 of the input velocity word, which is an
8 - b i t , signed two's complement, with a maximum value of plus or minus decimal 90, to
the position accumulator during each of the eight subcycles. The velocity word
is added in these small increments to provide a smoother motor operation.
a f . Operating cycle. The interpolator operating cycle is begun with the positive
t r a n s i t i o n o f t h e i n t e r r u p t r e q u e s t ( I R Q ) f r o m U 2 2 . T h e microprocessor responds and
the interpolator write (W26) latches the first half of the velocity word (bus 12-15)
i n t o o n e o f f o u r r e g i s t e r s o f t h e i n p u t d a t a r e g i s t e r U 2 5 a s selected by the address
bits (bus 0-1).
(1) The latching of data into U25 is accomplished during the Y-axis portion
of the eighth subcycle of the previous interpolator cycle. The-first subcycle
places the four least significant bits (LSB) of the X-axis instruction on the inputs
o f t h e d a t a s e l e c t o r U 2 6 . T h e data selector couples the X LSB to the Y inputs of
A t t h i s t i m e , t h e Z inputs are the four LSBs from the previous
t h e adder U24.
s u b c y c l e , i n p u t t h r o u g h U 2 1 . T h e output of U24 is the sum of the Y and Z inputs and
If a carry-out from the previous
the carry input (X) from the carry adder U27.
summation in U24 exists, it is clocked through U27 and becomes a carry-in to U24 for
the present subcycle. The carry input to U24 is set low every 16 clock pulses to
assure that the carry is clear at the beginning of each new cycle.
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