TM 5-6675-323-14
h . M y a d d r e s s . T h e address comparator U235 compares the logic levels of the
address switch settings with the first five data bits coupled through the bus
receivers U231 and U233 from the data input/output (010) lines DI01 through 0105.
If a valid address is on the bus, the logic levels of the two inputs will be equal,
a n d t h e a d d r e s s c o m p a r a t o r o u t p u t w i l l b e t r u e . T h i s output is the my address (MA)
signal which is used as an input to the talk U213A and listen U219B flip-flops.
H a v i n g received a valid address, the plotter has to decode the data bits on DI06 and
DI07 to determine if it is being addressed as an acceptor and set up its listen
logic, or as a source and set up its talk logic circuits. If the LISTEN ONLY switch
is in the listen only position, the talk circuits will be disabled regardless of the
data bits on DI06 and DI07.
i. Acceptor (Listen) handshake sequence. When the controller is ready to trans-
fer a control word on the data bus, it sends ATN true and EOI false.
C o n t r o l words
a r e a c c e p t e d b y t h e p l o t t e r w i t h o u t m i c r o p r o c e s s o r i n t e r v e n t i o n . W h e n the plotter
receives the above two signals, it starts the handshake sequence:
(1) The plotter indicates that it is ready to accept data by setting RFD true
and DAC false.
(2) After RFD has gone true, the controller places a data byte on the eight
data lines and sets the DAV true line.
( 3 ) After the DAV line has gone true, t h e p l o t t e r s e t s t h e R F D f a l s e , a c c e p t s
t h e data, and sets DAC true.
( 4 ) After the DAC line has gone true, the controller can set DAV false again
a n d t a k e t h e d a t a o f f t h e l i n e . W h e n DAV goes false, the plotter sets DAC back to
false, and the sequence is ready to repeat the handshake sequence.
j. When the controller sends a valid address with DI06 true and DI07 false, the
plotter is being addressed as a listener.
B i t decoder logic gates U221D and U215C
decode the true bit 6 and false bit 7 to provide a clock pulse; U235 provides the MA
i n p u t ; and gates U221A, U222B, and U212D decode bits 1 through 5 to provide unlisten
command to the K input of the listen flip-flop U219B. The Q output of the listen
f l i p - f l o p provides one input to the receive handshake gate U202A whose output is
read into the microprocessor through the gate U208 during an HP-IB read cycle. A
r e a d y (rdy) signal from the microprocessor and the levels of the DAV and ATN and the
Q output of the listen flip-flop U219B are decoded by U201A-D, U202A-C, U203F, and
U226B.
T h e decoded logic levels enable the bus handshake lines in the timing
sequence shown.
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