TM 5-6675-320-14
(2) The output from U24 is loaded into the four LSB registers of the X
accumulator U19.
The data transfer to U19 is accomplished when U19 is enabled by
the write enable decoder U10.
The decoder is enabled by the clock signal and a
write signal from control ROM U20.
(3) Having stored the X-axis LSB in U19, the X-axis most significant bits
(MSB) are loaded into the adder U24.
These are summed with the X MID SB from the
preceding subcycle and stored in the MID SB register of U19. With the next clock
pulse, the output of the data register remains constant. The data selector U26
couples the sign bit of the MSB to the Y input of the adder U24, while the MSB from
the previous subcycle is coupled to the Z input.
These bits and the sign bit are
summed and latched into the MSB register of U16 by the write enable decoder U10C.
This completes the updating of the X-axis accumulator for this subcycle .
(4) The output of the accumulators is used to address the sine/cosine ROMs
U9 and U15.
The four LSBs and the sign bit of the MSB are not used to address the
ROMs, but are retained for use in further computation. The output function of the
ROMs is controlled by the inputs to pins 14 and 15. See Table 4-16. ROM U9 gene-
rates the four LSB inputs to the digital to analog converter (DAC) U7, while U15
outputs the four MSBs to U7.
Table 4-16. ROM FUNCTIONS
PIN 14
PIN 15
ROM OUTPUT
Low
Low
Cosine, 3rd Harmonic
High
Low
Cosine Fundamental
Low
High
Sine, 3rd Harmonic
High
High
Sine Fundamental
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