TM 5-6675-320-14
Table 4-14. MICROPROCESSOR DEFINITIONS - Cont
Mnemonic
Name
D e f i n i t i on
FLG
FLAG
STS
STATUS
IFSTM
INSTRUCTION FETCH
START MEMORY
INTERRUPT (READ 10)
ACKNOWLEDGE
XSMC
EXTENDED SYNCHRONOUS
MEMORY COMPLETE
A self-test switch input which, when actu-
ated, causes system to go to the next step.
Indicates on power-up whether the system is
i n n o r m a l o p e r a t i o n o r s e l f - t e s t.
A signal where the rising edge denotes
address of an instruction.
Acknowledges that an interrupt has been
accepted.
Extends the SMC to allow time needed by MOS
memories to stabilize data.
s . C l o c k g e n e r a t o r.
The output of the crystal controlled 10 MHz oscillator
provides the clock input for the divide by two flip-flop U60A which in turn provides
two 5 MHz pulsed inputs to the clock driver circuit. The clock driver U63 outputs
are MOS level non-overlapping clock pulses referred to as phase 1 (PH1) and phase 2
(PH2). These two signals provide all timing for the plotter and the clock drive to
the microprocessor.
t .
M i c r o p r o c e s s o r.
Using the clock input, the microprocessor issues the appro-
priate timing signals to initiate and maintain the proper sequence of events re-
quired for processing data and instructions .
The activities of the microprocessor
are cyclical; fetching an instruction, performing the required operations, and then
fetching the next instruction in an orderly, timed sequence.
(1) The main timing signal from the microprocessor is start memory (STM),
indicating the start of a memory read cycle .
The falling edge of STM is used to
latch the memory address into the 3-state address latches U52 and U53. The rising
edge of synchronous memory complete (SMC) indicates the end of memory access cycle,
with the data being latched into either the microprocessor (READ cycle) or into RAM
(WRITE cycle). In order to satisfy the access time requirements of RAM and some of
the internal I/0 circuitry, SMC is extended by the use of unsynchronous memory
complete UMC to generate extended synchronous memory complete (XSMC). The micropro-
cessor bus is buffered by the use of bidirectional drivers U46 and U47. The MOS
(memory) bus is further isolated from the TTL bus by the use of bidirectional
drivers U49 and U50.
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