TM 5-6675-320-14
( 6 ) T h e c o m p u t e r i n t e r r u p t l o g i c c i r c u i t a l l o w s t h e H P - I B i n t e r f a c e to
r e q u e s t s e r v i c e , i . e . , t a l k t o t h e c o m p u t e r.
Before it can transfer data to the
computer, the HP-IB Interface must first notify the computer and request a transfer.
This circuit has two interrupt request lines to the computer, IRL and IRH. When an
i n t e r r u p t i s r e q u i r e d,
as when data from the HP-IB is to be processed, the processor
in the control logic circuit outputs a computer interrupt request (CIRQ) instruction
s i g n a l t o t h e c i r c u i t .
This signal induces the circuit logic to send an IRL or IRH
signal low .
Which signal goes low depends on which address the select code switch
in the select code decoder circuit is set.
If the switch is set between Ø and 7,
IRL is sent low.
If the switch is set between 8 and 15, IRH is sent low. When the
computer senses an interrupt request,
i t w i l l c o n d u c t a n i n t e r r u p t p o l l t o d e t e r m i ne
w h i c h o f i t s i n t e r f a c e s r e q u i r e s s e r v i c e.
A peripheral address bit (PAØ thru PA3)
will be received from the computer by the select code decoder circuit of the HP-IB
I n t e r f a c e .
If the bit matches the setting of the select code switch, then the
transfer cycle previously described is initiated in reverse and data in the I/0 data
r e g i s t e r c i r c u i t i s t r a n s f e r r e d t o t h e d a t a l i n e s.
The computer interrupt logic
c i r c u i t w i l l a l s o p u l l o n e o f t h e I / 0 d a t a l i n e s l o w .
NOTE
For a select code switch setting of 7, data line I0D7 should be
low.
See Table 4-3 for a complete list of interrupt request bits.
Table 4-3. INTERRUPT REQUEST BITS
Select Code
Line Pulled Low
Ø o r 8
1 o r 9
2 or 1Ø
3 or 11
4 or 12
5 or 13
6 or 14
7 or 15
IODØ
IOD1
I0D2
I0D3
I0D4
I0D5
I0D6
I0D7
(7) Communication between computer and plotter. The computer interrupt
l o g i c c i r c u i t a l l o w s t h e p l o t t e r t o b e c o m e t h e a c t i v e c o n t r o l l e r a n d i n t e r r u pt
o p e r a t i o n o f t h e p r o c e s s o r i n t h e c o n t r o l l o g i c c i r c u i t.
T h e i n t e r r u p t l o g i c is
enabled by an interrupt enable (IENA) signal from the control logic circuit.
4-13
