TM 5-6675-316-14
To initiate a flash, three conditions must be
(3) Flash control circuit.
satisfied:
Carriage must be low (CRRDY).
Flash Power Supply must be low (TDLY).
5D04 and FLXD8 signals must be low.
When these conditions are met, flip-flop F2 will set on the next MP signal. Nand
gate 3 requires two high inputs, CHEQ and flip-flop F2. This
ows a flash pulse
on the first dark part to clear transition after the MP. The FP = signal sets
flip-flop F3. This starts a 16 msec time delay (TDLY) = to allow the flash power
supply capacitors to recharge.
2-67
