TM 5-6675-316-14
(3) Address lines All, A12 and A13 are routed to the chip select decoder via
switch E/F2. There they are decoded into chip select 1ines (CEO thru CE7) to enable
a single row of RAMs (1K x 8-bit). Memory size is determined by the settings of
switches E/Fl-7 and E)F2. Address lines All, A12 and A13 are decoded by chip select
decoder to enable lK of RAM memory. For memory sizes smaller than 8K, various
combinations of All, A12, A13 and CE5, CE6, H7 are compared at the comparator. The
output of the comparator is used to enable or disable the address comparator. When
address lines All, A12 and A13 are not used for enabling RAMs, they are used as
part of the BOARD ENABLE. These signals are connected to memory size and address
comparators through E/F2-l (All), E/F2-5 (A12), and E/Fl-7 (A13) where they are
compared to E/Fl-l (All), E/Fl-2 (A12) and E/Fl-3 (A13). The remaining address
decode switches E/Fl-4, E/Fl-5 and E/Fl-6 are compared directly to A14, A15 and A16.
2-5O
