TM 5-6675-323-14
( 3 ) V o l t a g e o u t p u t s m o o t h i n g c i r c u i t . T h e voltage induced into the secondary
windings of transformer T4 is rectified in a conventional manner.
(a) A+5 V (A) supply is the output of full-wave rectifiers CR26 and
CR27 filtered by capacitor C24. A crowbar circuit provides over-voltage protection
t o the load by triggering SCR Q7 and clamping the +5 V (A) to common should an over-
v o l t a g e c o n d i t i o n o c c u r . T h e +12 V and -12 V supply is the output of modular diode
bridge CR22 which is connected across a center-tapped secondary winding of transfer-
mer T4.
Capacitor C19 provides filtering for the +12 V supply output and capacitor
C 2 0 provides filtering for the -12 V supply output. SCR's Q8 and Q9 provide over-
voltage protection for the load in a similar manner to the +5 V (A) output. The +7
V supply is developed by tapping in the low (case) side of a 5 V regulator (U3) to a
divider (R28 and R29), the junction of which is +2 V above common.
( b ) The +26 V and -26 V supply signals are outputted from a full-wave
bridge rectifier consisting of diodes CR18 thru CR21. Capacitors C17 and C18 pro-
vide filtering for the +26 V and -26 V supplies respectively. The switched output
v o l t a g e s , + 5 V ( A ) , - 1 2 V, +12 V, +7 V, +26 V, and -26 V, are connected to the
plotter circuits through PCA A11. The circuits that generate the drive pulses for
b o t h A9-Q1 and the chopper circuits are located on PCA A10 and will be described
next.
(4) Timing sawtooth waveform generation circuit. Generates a 36 kHz saw-
( a ) Transistors A10-Q8 and Q9 form a complementary Darlington config-
uration in which any base-to-emitter offset voltages generated as a function of
temperature change are minimized. Transistor A10-Q9 is the current source for
sawtooth-forming capacitor A10-C11. The rate of rise (ramp) in the collector cur-
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rent of Q9 determines the frequency of the generated sawtooth. Frequency adjustment
potentiometer A10-R35 sets the bias level of A10-Q8 and Q9, thus, establishing a
constant current through transistor A10-Q9.
(b) Reference voltage from the voltage divider circuit is provided by
voltage comparator U1A. The normally high input to the fault latch is pulled low by
open collector U1A-1 when an over-current condition is detected, thus, setting the
fault latch and disabling the pulse width modulator A10-U4B output.
( 5 ) V o l t a g e t u r n - o n r e g u l a t i o n c i r c u i t . Controls voltage buildup in switched
power circuits by regulating the initial turn-on drive pulse width to series pass
transistor A9-Q1.
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