TM 5-6675-320-14
h . H P - I B a d d r e s s r e g i s t e r.
The HP-IB address register consists of a hex, tri-
state buffer and six switches.
Five of the switches are used to set the five least-
s i g n i f i c a n t b i t s o f t h e H P - I B t a l k / l i s t e n a d d r e s s.
When each switch is off, its
corresponding bit is set to a logical 1.
The HP-IB address switches are connected
to the five least-significant bits of the processor data bus (DO through D4). In
addition to the HP-IB address switches, this module also contains the system
c o n t r o l l e r s w i t c h .
When this switch is on, the interface assumes the role of system
c o n t r o l l e r .
This switch is connected to bit D5 of the processor data bus. The
contents of this register are gated onto the processor data bus when the processor
issues a read interface bus address (RIBA) instruction .
i . D a t a i n p u t m u l t i p l e x e r.
The function of the data input multiplexer is to
route either a data byte (DI01 through DI08) or a control byte (EOI, ATN, SRQ, REN,
IFC, DAV, NRFD, and NDAC) from the HP-IB transceivers to the processor data bus.
The processor selects the data byte by issuing the read interface bus data (RIBD)
command.
The control byte is selected when the processor issues the read interface
bus control (RIBC) command.
j . H P - I B t r a n s c e i v e r s .
The interface uses four bus transceiver modules. Two
are used for the HP-IB data lines (DI01 through DI08) and two are used for the HP-IB
control lines (EOI, ATN, SRQ, REN, IFC, DAV, NRFD and NDOC). These transceivers
allow bidirectional flow of data and control information between the interface and
the HP-IB.
Each transceiver provides four open - collector drivers and four receivers
w i t h h y s t e r e s i s.
k . P a r a l l e l p o l l l o g i c.
T h e p a r a l l e l p o l l l o g i c p r o v i d e s t h e c a p a b i l i t y to
respond to a parallel poll conducted by the controller in charge of the HP-IB. When
the controller initiates a parallel poll (ATN and EOI true) and the calculator has
requested service from the controller via the SRQ line, the parallel poll logic
sends one bit of status to the controller via one data line (DI01 through DI08) .
l .
I n i t i a l i z e c i r c u i t .
The initialize circuit applies +9 V to the processor
after all other power supplies are stable.
This condition is indicated by the
initialize signal (INIT) from the calculator, and causes the processor to execute an
i n i t i a l i z e a l g o r i t h m .
I f t h e i n t e r f a c e i s t h e s y s t e m c o n t r o l l e r , t h i s a l g o r i t hm
issues the abort message (IFC) and sets the REN line true.
I f t h e i n t e r f a c e i s n o t
t h e s y s t e m c o n t r o l l e r , t h i s a l g o r i t h m c l e a r s a l l H P - I B I n t e r f a c e f u n c t i o n s . T h is
circuit also provides a reset pulse to the HP-IB control bus latch.
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