TM 5-6675-320-14
(2) The calculator command register consists of a 4-bit latch and four open-
collector nand gates.
The latch holds the I/O register code (R4 through R7) deter-
mined by IC1 and IC2 and the direction of the I/O transfer determined by DOUT. In
addition, one bit of the latch is always set when the calculator requests an I/O
o p e r a t i o n .
This bit is buffered through one of the nand gates and becomes the
c a l c u l a t o r f l a g l i n e ( C F L G ) .
Setting this line true causes the flag line (FLG) to
g o h i g h , i n d i c a t i n g t h a t t h e i n t e r f a c e i s b u s y .
The other three nand gates are used
to gate the DOUT, IC1, and IC2 signals onto the processor’s data bus when it issues
a read calculator command register (RCCR) instruction.
When the processor has
executed the requested I/O operation and is ready for another I/O operation, it
issues a clear calculator command register (CCCR) instruction, which clears the
calculator command register and readies the interface for another I/O operation.
c .
C a l c u l a t o r I / O d a t a r e g i s t e r s.
The calculator output data register consists
of two 4-bit latches and eight open-collector nand gates. This register holds the
data to be transferred from the calculator to the interface. The data contained in
the latches is gated onto the processor data bus when the processor issues a read
calculator output data (RCOD) instruction.
The calculator input data register consists of two 4-bit latches and eight open-
collector nand gates .
The data on the processor data bus is latched into the two 4-
bit latches when the processor issued the send calculator input data (SCID) command.
T h e d a t a i n t h i s r e g i s t e r i s t r a n s f e r r e d t o t h e c a l c u l a t o r i n p u t / o u t p u t d a t a l i n es
when the calculator requests an input operation.
d . C a l c u l a t o r i n t e r r u p t l o g i c ,
T h e c a l c u l a t o r i n t e r r u p t l o g i c a l l o w s t he
interface to request service from the calculator .
T h e c a l c u l a t o r i n t e r r u p t l o g i c is
a network of gates and a one-of-eight decoder.
T h i s l o g i c p u l l s t h e a p p r o p r i a te
interrupt request line (IRL or IRH) low when the processor issues a calculator
interrupt request (CIRQ) instruction and the calculator is not conducting an
i n t e r r u p t p o l l ( I N T ) .
IRL is pulled low when the select code switch is set to an
address between 0 and 7, and IRH is pulled low when the switch is set between 8 and
15. When the calculator senses a service request, it conducts an interrupt poll to
determine when interface requires service .
A poll is conducted when INT is low.
When the most-significant address bit from the select code switch, the calculator
i n t e r r u p t l o g i c p u l l s o n e o f t h e c a l c u l a t o r i n p u t / o u t p u t d a t a l i n e s l o w . T he
setting of the select code switch determines which line is pulled low, as shown.
Interrupt Request Bits
Select Code
Line Pulled Low
0 o r 8
1 o r 9
2 or 10
3 or 11
4 or 12
5 or 13
6 or 14
7 or 15
IODØ
IOD1
IOD2
IOD3
IOD4
IOD5
IOD6
IOD7
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