TM 5-6675-320-14
e.
C o n t r o l l o g i c.
The processor, ROM I/O register selector, and oscillator form
t h e c o n t r o l l o g i c p o r t i o n o f t h i s i n t e r f a c e.
The processor controls all interface
operations by issuing instructions via seven control lines, the 8-bit processor data
b u s , a n d s e l e c t i n g I / O r e g i s t e r s v i a t h e I / O r e g i s t e r s e l e c t o r . T h e a l g o r i t h m s f or
interface control and the implementation of the HP-IB interface functions are
contained in the 4096-bit ROM.
The oscillator generates a 2 MHz (approx.)
asymmetrical waveform which is used as the main clock for the processor and as the
e n a b l e s i g n a l f o r t h e I / O r e g i s t e r s e l e c t o r .
f . P r o c e s s o r i n t e r r u p t l o g i c .
The processor interrupt logic is a network of
gates that provides the ability to interrupt the processor for either of two
c o n d i t i o n s:
when an abort message (IFC) is received from the HP-IB, or when the
control line ATN is set true by the controller in charge.
(1) An interrupt occurs for the second condition only when the calculator is
n o t t h e a c t i v e c o n t r o l l e r.
(2) The processor enables the interrupt logic via the interrupt enable
(IENA) line.
When an abort message is received via the HP-IB, the interrupt causes
the processor to generate a 100 microsecond pulse on the IFC line and then initial-
izes all of the HP-IB interface functions within the interface. The IFC line was
previously set true as the result of an I/O operation from the calculator.
(3) When the interface is not the active controller, the processor not only
enables the interrupt logic via the interrupt enable line, but also sets the immediate
c o n t r o l l i n e ( I M D ) t r u e .
When an abort message is received, the interrupt logic
generates a vectored interrupt to the algorithm which initializes all of the HP-IB
i n t e r f a c e f u n c t i o n s .
In addition, when the controller in charge of the HP-IB sets
the ATN line true, the interrupt logic immediately clears the HP-IB output data
latch and disables the HP-IB transceivers for the HP-IB data lines (DIOI through
DI08), the DAV line, the NRFD line, and the EOI line; then the NDAC line is set low.
This leaves the interface ready to receive data from the controller. A vectored
interrupt is also generated to the algorithm which controls the acceptance and
analysis of the data sent by the controller.
g .
HP-IB output data and control bus latches.
(1) The HP-IB output data latch consists of two 4-bit latches. Data is
transferred from the processor data bus into this 8-bit latch when the processor
issues the send interface bus data (SIBD) command. The outputs of this latch are
routed to the HP-IB data lines via the drivers contained in the HP-IB transceivers.
(2) The HP-IB control bus latch is a 5-bit latch which holds the bit pattern
to be applied to the HP-IB control lines (EOI, ATN, SRQ, REN, and IFC). The appro-
priate bit pattern is transferred from the processor data bus into this latch when
the processor issues the send interface bus control (SIBC) command. This latch
consists of one 4-bit latch and one D flip-flop. The outputs of this latch are
routed to the bus drivers contained in the HP-IB transceivers.
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