TM 5-6675-320-14
NOTE
Operation of the HP-IB Interface ROM is explained in the following
paragraphs in terms of the type of function being performed.
( b ) M o n i t o r i n g s i g n a l l i n e s .
In order to determine its mode of opera-
tion, the HP-IB Interface ROM has a processor in the control logic circuit that
monitors the signal lines from the computer and the plotter.
(c) Monitoring of the computer is accomplished via a calculator flag
(CFLAG) signal from the computer command register circuit. When the computer
requests an input/output (I/0) operation from the HP-IB Interface, the CFLAG signal
i s s e n t t r u e .
A true CFLAG signal induces the processor in the control logic
circuit to send instructions to other circuits to decode and execute the requested
I / 0 o p e r a t i o n.
(d) To monitor the plotter for an I/O operation request, the processor
i n t h e c o n t r o l l o g i c c i r c u i t p e r i o d i c a l l y s a m p l e s s i g n a l s o n t h e c o n t r o l l i n e s a n d
t r a n s f e r l i n e s .
If the state of these signals indicates an operation is requested,
the processor issues appropriate instructions.
(3) Select code decoder circuit determines initially when the HP-IB Inter-
face ROM is being addressed by the computer.
A select code switch in the circuit
establishes a unique select code for the HP-IB Interface ROM, which will only
respond when an identical code is sent on peripheral address lines PAØ thru PA3.
The circuit sends calculator flag (CFLAG) signal low to indicate its presence and
readiness to the computer and sends status (STS) line low to tell the computer that
n o e r r o r c o n d i t i o n s e x i s t.
T h e c i r c u i t r e s p o n d s t o t h e r e c e i p t o f a c o r r e c t a d d r e s s
code by looking for an I/0 command via the I/0 register decoder circuit.
( 4 ) I / 0 r e g i s t e r d e c o d e r c i r c u i t c o n t a i n s a s e t o f g a t e s t h a t i n t e r p r e t an
I/0 command from the computer.
A direction of transfer (DOUT) signal indicates to
the circuit whether a transfer is an input or output operation from the computer,
i.e., whether data will be transferred to or from the HP-IB Interface.
If a data
transfer to the HP-IB Interface is indicated, the circuit latches any data on the
I/0 data lines IODØ thru IOD7 into the output register of the I/0 data register
circuit with an I/0 strobe pulse (IOSB) signal.
The IOSB signal also induces the
latching of any coded signals on the DOUT, IC1, and IC2 lines into the computer
command register circuit.
If the HP-IB Interface ROM were transferring data to the
computer (from the HP-IB Interface), the circuit would operate in the opposite
direction upon receipt of the IOSB signal.
Data would be latched onto the computer
data lines IODØ thru IOD7.
NOTE
Data cannot be inputted to the computer when it is conducting an interrupt
p o l l .
The INT signal is low for an interrupt poll.
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