TM 5-6675-318-14
h. HP-IB address register. The HP-IB address register consists of a hex, tri-
state buffer and six switches.
Five of the switches are used to set the five least-
significant bits of the HP-IB talk/listen address. When each switch is off, its
c o r r e s p o n d i n g b i t i s s e t t o a l o g i c a l 1 . T h e HP-IB address switches are connected
to the five least-significant bits of the processor data bus (D through D4). In
addition to the HP-IB address switches, this module also contains the system
controller switch. W h e n t h i s s w i t c h i s o n , t h e i n t e r f a c e a s s u m e s t h e r o l e o f s y s t e m
controller.
This switch is connected to bit D5 of the processor data bus. The
contents of this register are gated onto the processor data bus when the processor
issues a read interface bus address (RIBA) instruction.
i.
Data input multiplexer. The function of the data input multiplexer is to
r o u t e either a data byte (DIO1 through DIO8) or a control byte (EOI, ATN, SRQ, REN,
I F C , DAV, NRFD, and NDAC) from the HP-IB transceivers to the processor data bus.
The processor selects the data byte by issuing the read interface bus data (RIBD)
command. T h e c o n t r o l b y t e i s s e l e c t e d w h e n t h e p r o c e s s o r i s s u e s t h e r e a d i n t e r f a c e
b u s control (RIBC) command.
j.
H P - I B t r a n s c e i v e r s . T h e interface uses four bus transceiver modules. Two
are used for the HP-IB data lines (DIO1 through DI08) and two are used for the HP-IB
c o n t r o l lines (EOI, ATN, SRQ, REN, IFC, DAV, NRFD and NDOC). These transceivers
allow bidirectional flow of data and control information between the interface and
t h e HP-IB.
Each transceiver provides four open-collector drivers and four receivers
with hysteresis.
k.
P a r a l l e l poll logic.
The parallel poll logic provides the capability to
respond to a parallel poll conducted by the controller in charge of the HP-IB. When
the controller initiates a parallel poll (ATN and EOI true) and the calculator has
requested service from the controller via the SRQ line, the parallel poll logic
sends one bit of status to the controller via one data line (DIO1 through DI08).
The initialize circuit applies +9 V to the processor
l.
Initialize circuit.
after all other power supplies are stable. This condition is indicated by the
i n i t i a l i z e s i g n a l ( I N I T ) f r o m t h e c a l c u l a t o r , a n d causes the processor to execute an
i n i t i a l i z e algorithm. I f t h e i n t e r f a c e i s t h e s y s t e m c o n t r o l l e r , t h i s a l g o r i t h m
If the interface is not
issues the abort message (IFC) and sets the REN line true.
the system controller, this algorithm clears all HP-IB Interface functions. This
circuit also provides a reset pulse to the HP-IB control bus latch.
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