TM 5-6675-318-14
PCA A5 INTERPOLATOR WRITE MODE OPERATION SEQUENCE
Sequence
Step
Circuit Operation
1
Read/Write register U9. When the interpolator write line of the
control bus goes low, i t e n a b l e s t h e w r i t e f u n c t i o n o f r e g i s t e r s
D a t a buses 12-15 are latched into one of four registers
U9-12.
s e l e c t e d by two address bits on buses and 1.
At start of interpolator operating cycle, registers U9-RB and RA
are low and four least significant bits (LSB's) of the X-axis in-
struction appear on both the output pins of register U9 and input
pins of data selector U17.
2
Data selector U17. High input select signal from U17 transfers X-
L S B to full adder U18.
3
F o u r - B i t and carry adder U18 and U19. Output of full adder U18 is
t h e sum of X-LSB from previous instruction stored in accumulator
T h e summation is then transferred to X-LSB register in accu-
U27.
mulator U27.
4
W r i t e enable decoder U10.
T h e data transfer from full adder U18 to
X - a c c u m u l a t o r U27 is initiated by gating clock pulse through nand
g a t e from U20 to U10.
W r i t e signal from ROM control gates clock
U 1 0 goes low and enables write func-
p u l s e through nand gate U10.
tion of accumulator U27.
5
Accumulators U27 and U28.
H a v i n g stored X-LSB in accumulator U27,
X - M S B is now clocked through data latch U9 and data selector U17 to
i n p u t s o f a d d e r U 1 8 . A t same time, MID-SB signal from accumulator
U27 is clocked through data selector U26 to inputs of adder U18.
Output of adder U18 is restored in MID-SB of accumulator U27.
6
W i t h next clock pulse, output of register U9 remains same while
select input to data selector U17 couples MSB sign bit (line 6) to
i n p u t s o f a d d e r U 1 8 . A t same time, four MSB's are coupled from U28
t h r o u g h U26 to inputs of adder U18. Output of adder U18 is now
l a t c h e d into MSB of U28.
This completes first subcycle, and output
o f accumulators U27 and U28 remains constant while data is being
t r a n s f e r r e d into sine/cosine ROM's U29 and U30. Four LSB's and
MSB's (sign bits) are discarded.
Sine and cosine only memories U29 and U30. Output function of
7
sine/cosine ROM's U29 and U30 is selected by state of inputs from
Outputs from ROM U30 make up four LSB inputs to
control ROM U20.
digital-to-analog converter (DAC) U12 while the outputs from ROM
U 2 9 provide four MSB inputs to DAC U12.
3-30
