TM 5-6675-318-14
C o n t a i n s octal
addresses 77-
(4) Read only memory 32 word constants.
The eight least
7737 . T h e 32 word constants are located in ROM's U7 and U6.
s i g n i f i c a n t b i t s ( L S B ' s ) , B U S 0 thru BUS 7, are located in U7,
and the eight most
s i g n i f i c a n t bits (MSB's), BUS 8 thru BUS 15, are located in U6.
Address lines ADR
t h r u ADR 4 are used to address both ROM's.
T h e low enable chip select (CS) for the ROM's is derived from BUS 8, BUS 13, BUS 14,
read memory (RDMEM), and synchronous memory complete (SMC) signal lines.
The criteria for selecting ROM 32 word constants is as follows:
A d d r e s s 8 high
A d d r e s s 13 low
A d d r e s s 14 low
Read memory (RDMEM) high
Synchronous memory complete (SMC) high
U 4 provides a
T h e s e s i g n a l s , i n p u t t e d to U2, U11, and U4, decode as ROM 32 select.
c h i p select to ROM's U6 and U7 and disables bidirectional interface bus (BIB) driv-
ers U5 and U10, leaving the bus lines clear for ROM output.
Is
functionally
divided
into
two
circuits:
c.
I n t e r n a l I/O PCA card A5.
I/O
circuits
Interpolator
circuits
Provide an interface between the front panel, interpolator
(1) I/0 circuits.
c i r c u i t s , and PCA A3. T h e y p e r f o r m t w o m a j o r f u n c t i o n s :
Processor
decoding
Processor
interrupt
3-28
