ARMY TM 5-6675-238-14
MARINE CORPS TM 08839A-14/1
assembly A3. Control over the SPU loop closer func-
tions is via the computer serial data bus. The serial data
bus consists of the signals listed in table 6-1. The
computer addresses a specific section in the SPU. The
address word is accumulated in a 17-bit register (16 bits
plus parity) and is decoded by the timing and control
logic. The timing and control logic sets up the signal to
enable decoding at the proper times. Only the section
whose fixed address corresponds to the address word
just received will become active, See figure 6-1 for
address word format, The section that is activated is
one that corresponds to the main address, subaddress,
and mode control bits of the address word. The ad-
dresses for the SPU are shown in table 6-2. Once a
section is activated, it is put into a mode of operation
for either receiving or transmitting data. When a sec-
tion is activated, the data envelope control signal is sent
from the computer, or the address alone is sufficient and
no data follows. If the data word to the specific section
in the SPU has a parity error, an error flag will be sent
and the data will not be used. The parity error will be
placed into an assigned bit position in the parity status
word (see figure 6-1) by the timing and control logic.
The parity status word will only be processed by the
SPU upon request from the computer for parity status
(see table 6-2). If any address word from the computer
has a parity error, the SPU address parity error latch is
set. This error is sent back to the computer via the
status register as bit 5 of the parity status word. No
section in the SPU is activated if an address word parity
error occurs except for the parity-error indicator. Suc-
cessive addresses without parity error will be processed
normally. The computer must periodically check to
ensure that no address parity has occurred; otherwise
data sent to the SPU following an address parity error
would be ignored. Once the computer checks for parity
errors, all the data parity latches as well as the address
parity error latch are reset and normal information flow
is restored.
b. Serial Data Bus Loop Closer. The serial data bus
loop closer is functionally illustrated in figure FO-3 and
is contained on logic no, 3 electronic component assem-
bly A3. The loop closer address word is received from
the computer by differential line receivers, providing no
parity error has occurred. The loop-around circuitry
decodes the address word and transmits the inverted
address word back to the computer as data. Logically,
the bits are inverted, but, electrically, the transmitted
word is identical to the address word. The computer
sends out positive logic with odd parity and receives
negative logic with even parity, The transmission is
synchronized by the clock and data envelope signals
from the computer. The bits in the address word which
activate the loop closer function are bit 0 in state 1, bit
1 in state 0, bit 2 in state 0, and bit 15 in state 1. All
other bit positions in the address will be variable under
computer control.
c. Loop Closer. The loop closer is
functionally illustrated in figure FO-4 and is contained
on logic no. 3 electronic component assemblv A3. The
signals from the computer repre-
sent gyroscope torquing rates and are applied to differ-
ential line receivers in the SPU, The ,and
generator in the SPU convert these torquing rate
signals into velocity signals These
velocity signals are transmitted from differential line
drivers to the computer, The differential line drivers are
tristate devices and are operated in a continuous enable
mode. A 2.4-kHz clock is generated in the SPU to
synchronize the generators, The
2.4-kHz clock is also sent to the computer to synchro-
nize various functions. The loop closer circuitry
operates continuously under computer program control
and does not need any external control from the serial
data bus,
d. Digital/DC Loop Closer. The digital/DC loop
closer is functionally illustrated in figure FO-5 and is
contained on logic no. 2 electronic component assembly
A2. The computer sends a specific address via the serial
data bus control logic to activate the digital/DC loop
closer circuitry. The computer then sends the specific
14-bit digital word that will be converted to analog.
Upon receipt of the correct address word with no parity
errors, the active and receive enable lines from the
serial data bus control logic are activated. In addition,
bit 15 of the data word is utilized to select either the V
lamp line from the computer or the digital/DC con-
verter output for the lower gyro temperature signal to
the computer. A relay is used to perform the switching
of the selected signal. The 14-bit data word from the
computer is converted to an analog signal and routed
back to the computer for comparison. The computer
compares the original data word with the data word just
received and then activates a failure flag if a no-go
condition is evident. V lamp is an analog signal that is
compared to the returned analog signal within the
computer, A no-go is flagged if the comparison is not
correct, If all analog signals are within tolerance of the
expected values, the computer is considered to be
operating correctly in this area and the next test is
started. For computer protection, no converter output
can go to the computer until computer + 5V is de-
tected,
e. Digital/Resolver and Digital/Synchro Loop
Closer. The digital/resolver and digital/synchro loop
closer is functionally illustrated in FO-6 and is con-
tained on logic no, 2 electronic component assembly
A2. The computer sends an address to activate the
digital/resolver and digital/synchro loop closer circui-
try, then sends a 4-bit angle which is to be used for the
test. Upon receipt of the correct address with no parity
errors, the active and the receive enable lines are
activated. In addition, bits 10, 11, and 12 of the address
word are decoded and used to select the phase of the
26-VAC reference signal. The data word is sent to the
6-2
