TM 5-6675-323-14
(g) The HP-IB address register circuit assigns five least significant
b i t s of the HP-IB talk/listen address to data on the processor data bus and enables
the HP-IB Interface to become the active controller, i.e., take over a transfer.
Six switches in the circuit are used to set the HP-IB talk/listen address. When
each switch is on, its corresponding bit is set to a logical . Five of these
s w i t c h e s are connected to the processor data bus bits D thru D4. One of the
s w i t c h e s is the system controller switch which, when on, makes the HP-IB Interface
the active controller for any data on the bus.
The output of the system controller
switch is connected to bit D5 of the processor data bus. T h e H P - I B t a l k / l i s t e n
address bits and system controller bit are gated onto the bus during a transfer
cycle when a read interface bus address (RIBA) is received from the control logic
circuit.
(h) Data from the I/O data register circuit is transferred via the
processor data bus to the HP-IB output latch circuit and to the ROM in the control
l o g i c c i r c u i t . T h e processor outputs a send interface bus data (SIBD) signal to
enable transfer of the data to an eight-bit latch in the circuit. A f i v e - b i t
pattern (HP-IB talk/listen address) that identifies the data is sent, with the send
interface bus control (SIBC) signal, to the HP-IB control bus latch circuit.
(i) When the HP-IB control bus latch circuit receives an SIBC signal,
the bit pattern on the processor is transferred to a five-bit latch. The outputs of
this latch are five signals (IE01, IATH, IRSQ, IREH, and IIFC), which are routed to
bus drivers in HP-IB transceiver circuit.
(5) The HP-IB transceiver circuit applies the identification bit pattern to
the five control lines (E0I, ATN, SRQ, REN, and IFC) of the signal lines. The
circuit has four bus transceiver modules, two for the data lines and two for the
control and transfer lines. They allow bidirectional flow of data and control
information via open collector drivers and receivers with hysteresis.
W h e n data and
bit patterns are transferred, they are sent by circuit to the plotter via the HP-IB
cable.
( a ) T r a n s f e r r i n g t o c o m p u t e r . W h e n data signals and the accompanying
control information is to be transferred from the plotter to the HP-IB Interface,
signals are first input to the circuit transceivers of the HP-IB transceiver
circuit.
(b) If a transfer from the plotter is processed, data and control bytes
are routed by the HP-IB input multiplexer circuit. Outputs of the transceivers
(data and control signals) are transferred through the circuit to the processor data
bus.
HP-IB transceiver circuit transfers a data byte (DI01-DI08) or a control byte
(E0I, ATN, SRQ, REN, IFC, DAV, NRFD, and NDAC) to the bus, depending on which
c o m m a n d s i g n a l i t r e c e i v e s f r o m c o n t r o l l o g i c c i r c u i t . O n e of two possible signals
are sent by the processor via its I/O register selector to HP-IB input multiplexer
circuit.
A data byte is transferred upon receipt of a read interface bus data
( R I B D ) command signal.
A read interface bus control (RIBC) command signal imple-
m e n t s a c o n t r o l b y t e t r a n s f e r . W h e n RIBD is received, a data byte is sent via the
processor data bus to the I/O data register circuit and latched by a send interface
bus data (SCIB) signal from processor for a transfer to the computer.
(c) A control byte is interpreted and implemented according to the
instructions for the HP-IB functions stored in the 4096-bit ROM of the control logic
circuit.
3-12
