TM 5-6675-323-14
(a) A latch in the computer command register circuit holds an I/O
T h e I/O register code is composed of bits
register code signal (bits R4 thru R7).
of the IC1 and IC2 signals and the transfer direction of transfer (DOUT) signal.
O n e bit of the register code is buffered through a nand gate to become the calcula-
tor flag (CFLAG) signal sent to the processor in the control logic circuit. If the
HP-IB Interface ROM is busy and cannot accomplish a transfer, CFLAG signal is sent
t r u e . C F L A G is sent to induce the interface flag (FLG) signal, sent to the computer
by the select code decoder circuit, to go high indicating the not-ready state of the
HP-IB Interface.
(b) When a transfer is first requested, the HP-IB Interface is not
operating and the CFLAG signal is false, enabling a low FLG signal to be sent
i n d i c a t i n g r e a d i n e s s . As soon as the I/O strobe pulse (IOSB) strobes the data,
D O U T , IC1 and IC2 signals into the HP-IB Interface, the computer command register
c i r c u i t s e n d s C F L A G s i g n a l t r u e . T h e HP-IB Interface ROM now cannot accept a second
set of data until the first is processed.
( c ) T r a n s f e r r i n g t o p l o t t e r . When coded signals and data have been
latched into the HP-IB Interface ROM, transfer operations begin. A true CFLAG
signal (same signal sent to the computer command register circuit) is sent to the
processor in the control logic circuit, to tell it an I/O operation is commanded.
The control logic circuit returns a read calculator command register (RCCR) signal
that causes ICI, IC2, and DOUT signals to be gated onto the processor data bus.
NOTE
After an I/O operation (data transfer) is completed, processor outputs a
clear calculator command register (CCCR) signal that clears circuits for
Calculator flag (CFLAG) is sent false to indicate
another operation.
readiness.
(d) After the processor in the control logic circuit outputs the read
calculator command register (RCCR) signal to computer command register circuit, it
RCOD
sends a read computer output data (RCOD) signal to I/O data register circuit.
gates data from the computer onto the processor data bus.
(e) If data were being transferred to the computer instead of from, the
processor would output a send computer input data (SCID) signal which would latch
data on its data bus into the I/O data register circuit, where it would wait for an
I/O strobe pulse to send it to the computer.
(f) The initialize circuit applies +9 V to the processor after all
other supplies are stable. An initialize (INIT) signal is received from the compu-
ter when the proper power conditions have been reached. If the INIT signal is
received and the HP-IB Interface is the active controller, the processor issues an
If the HP-IB
abort signal (IFC) and sends a remote enable (REN) signal true.
Interface is not the controller, the processor clears all the HP-IB functions. The
initialize circuit also provides a reset pulse for the HP-IB control bus latch
circuit and power for the control logic circuit.
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