TM 5-6675-318-14
Table 3-14. MICROPROCESSOR DEFINITIONS - Cont
Name
Definition
Mnemonic
A self-test switch input which, when actu-
FLG
FLAG
ated, causes system to go to the next step.
STS
STATUS
I n d i c a t e s on power-up whether the system is
in normal operation or self-test.
A signal where the rising edge denotes
INSTRUCTION FETCH
IFSTM
address of an instruction.
START MEMORY
A c k n o w l e d g e s that an interrupt has been
IAK
INTERRUPT (READ 10)
accepted.
ACKNOWLEDGE
XSMC
Extends the SMC to allow time needed by MOS
EXTENDED SYNCHRONOUS
memories to stabilize data.
MEMORY COMPLETE
Clock generator. The output of the crystal controlled 10 MHz oscillator
s.
provides the clock input for the divide by two flip-flop U60A which in turn provides
two 5 MHz pulsed inputs to the clock driver circuit. The clock driver U63 outputs
a r e MOS level non-overlapping clock pulses referred to as phase 1 (PH1) and phase 2
These two signals provide all timing for the plotter and the clock drive to
(PH2).
the microprocessor.
t . Microprocessor.
Using the clock input, the microprocessor issues the appro-
priate timing signals to initiate and maintain the proper sequence of events re-
quired for processing data and instructions. The activities of the microprocessor
a r e c y c l i c a l ; fetching an instruction, performing the required operations, and then
fetching the next instruction in an orderly, timed sequence.
(1) The main timing signal from the microprocessor is strat memory (STM),
i n d i c a t i n g t h e s t a r t o f a m e m o r y r e a d c y c l e . T h e falling edge of STM is used to
l a t c h the memory address into the 3-state address latches U52 and U53. The rising
e d g e of synchronous memory complete (SMC) indicates the end of memory access cycle,
with the data being latched into either the microprocessor (READ cycle) or into RAM
In order to satisfy the access time requirements of RAM and some of
( W R I T E cycle).
t h e internal I/O circuitry, SMC is extended by the use of unsynchronous memory
c o m p l e t e UMC to generate extended synchronous memory complete (XSMC). The micropro-
cessor bus is buffered by the use of bidirectional drivers U46 and U47. The MOS
(memory) bus is further isolated from the TTL bus by the use of bidirectional
d r i v e r s U49 and U50.
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